ESA GNC Conference Papers Repository

Miniaturized High Performance MEMS Accelerometer Detector
Gonseth, S.; Eichenberger, C; Durrant, D; Airey, P
Presented at:
Porto 2014
Full paper:

In the framework of the demonstration of European capabilities for future space exploration mission, a high performance miniaturized MEMS accelerometer detector is developed by Colibrys for incorporation into compact IMU (Inertial Measurement Unit). The envisaged missions where a miniaturized IMU is under development by SEA should cover: <br><br>Aerobraking <br><br>Entry, Descent and Landing (EDL) <br><br>Planetary Rovers Navigation The accelerometer specifications were defined through an ESA study by providing accelerometer component as well as system level requirements for most future planetary application. Based on these needs, the feasibility of a MEMS, high accuracy, low power and miniaturized accelerometer has been successfully demonstrated with an available sensor designed for aerospace market. The development toward TRL5 of a RadHard MEMS accelerometer is led by Colibrys, and will be made available on the open market for incorporation into Inertial Measurement Units and standalone 1 & 3 axis accelerometer devices. This activity covers the development of the radiation hardened ASIC managed by HMT, the design of a fully hermetic ceramic package and a full characterisation test of the accelerometer component. The key parameters are: <br><br>Analogue outputs (acceleration and temperature) <br><br>Dual range independent range: ±1g & ±20g <br><br>White noise: 5µg/?Hz <br><br>Power supply 3.3V / Power consumption per channel: 10mW <br><br>Non linearity: 0.2% / bandwidth: 100Hz <br><br>100Krad radiation tolerance This paper develops the accelerometer performance, lifetime and environmental requirements. The on-going accelerometer component design and technology will be presented as well as the planned accelerometer testing. The results of a preliminary radiation test (SEE & TID) performed on a test chip ASIC will be discussed and the select ASIC architecture with digital redundancy will be shown.