ESA GNC Conference Papers Repository

The extensive use of MEMS and CMOS technologies in the past ten years allowed a huge miniaturisation of electro-optical equipment, associated with a marked increase in capabilities. This is well seen in the consumer electronics industries, e.g. the emergence of micro-miniature auto-focus photographic cameras in mobile phones. ESA technology developments are facing this miniaturisation trend, with the start of real MEMS applications in space (e.g. MEMS rate sensor, micro shutters and micro thrusters) and highly-integrated CMOS image sensors such as the LCMS. This technology development is now reaching a maturity level suitable to make attitude sensors ‘on a chip’ feasible. In the frame of an ESA contract, Galileo Avionica, together with Thales Alenia Space, Cypress Semiconductor and BAE system were involved in the feasibility study for the application of micro-technologies to attitude sensors like sun sensors, star trackers and navigation cameras. The industrial team set up for this study covers the different areas of know how, ranging from optical MEMS application, electro-optical CMOS devices, system-on-a-chip integration, attitude sensor development, assembly and characterisation, and satellite prime contractors, so that all the design aspects can be properly addressed. Scope of the work is to define the achievable electronics miniaturisation, the extent of replacement of standard optics with MEMS for size reduction purposes, together with the definition of the production, packaging, and testing activities flow. Based on already performed activities, the design of a Sun Sensor on chip has been considered as the most straightforward to be developed in a short/medium period, and therefore the design activities on the Sun Sensor have been pushed with respect to star sensor and navigation camera. In this paper, an overall description of the adopted key trade off, together with the highlight of the defined sensor architectures and relevant design main parameters are reported. The paper identifies the key areas of technological challenge and feasibility issues that are likely to affect most SoC developments from technological, industrial and economical viewpoint. A SoC outline design with expected performances is presented, together with a discussion on development planning and difficulties.